1. Field of the Invention
This invention relates to an improvement in the internal wiring of semiconductors in a Darlington amplifier configuration and more particularly, to a Darlington amplifier configuration in which speed-up diodes are connected between the base of the front-stage transistor(s) and the base of the rear-stage transistor(s) to allow for better current distribution in the base region of the rear-stage transistor(s) during periods of abrupt changes in device current density.
2. Description of the Related Art
To make a large capacity transistor, a plurality of individual transistors are connected to form a Darlington configuration. This configuration typically consists of rear stage transistor(s) and front stage transistor(s). One advantage of the Darlington configuration is that the gain of the combination of the two stages is the product of the gain of each of the multiple transistors comprised within the stages. Furthermore, each of the transistors within the stages can be optimized for power handling capability, gain, frequency response and/or other parameters of interest.
In typical prior art examples, in a multiple transistor configuration, the base of the rear-stage transistor of the Darlington circuit is connected with the base of the front-stage transistor via a speed-up diode to shorten the turn-off time. Equivalent circuits of such Darlington configurations are shown in FIGS. 2(a) and 2(b).
A Darlington amplifier consisting of two transistors is shown in FIG. 2(a). Here a speed-up diode 21 has its cathode connected to the base of NPN transistor 11. This diode 21 is connected in a forward direction between the base of the rear-stage, or output stage, NPN transistor 12 and the base of the front-stage, or input stage, NPN transistor 11.
A Darlington amplifier comprising three transistors is shown in FIG. 2(b), where a first speed-up diode 21 is connected in a forward direction between the base of the second-stage NPN transistor 12 and the base of the first-stage NPN transistor 11. A second speed-up diode 22 is connected in a forward direction between the base of the final-stage, or output-stage, NPN transistor 13 and the base of the front-stage transistor 11.
FIGS. 3(a) and 3(b) show chip level electrical interconnections of the Darlington configurations which are shown schematically in FIG. 2. The interconnections shown in FIG. 3 are bonded to the semiconductor material constituting the Darlington structure.
Referring to FIG. 3(a), in the Darlington amplifier configuration comprising the two transistors, a base terminal B is connected to the base 32 of the rear-stage transistor via speed-up diode 21 and aluminum leads 4. Base 32 also acts as the emitter of the front-stage transistor and is connected to base 31 of the front-stage transistor and the speed-up diode 21 by aluminum leads 4. Bases 31 and 32 are both positioned on semiconductor chip 1. An emitter terminal E is connected to the plural emitters 33 of the rear-stage transistor by aluminum leads 4.
Referring to FIG. 3(b), in the Darlington amplifier comprising three transistors, a base terminal B is connected to the base 32 of the second-stage transistor serving also as the emitter of the front-stage transistor, via the base 31 of the front-stage transistor and the speed-up diode 21 with aluminum leads 4. Also, the base terminal B is connected to the base 34 of the final-stage transistor via the speed-up diode 22 and aluminum lead 4, acting also as the emitter of the second-stage transistor. An emitter terminal E is connected to the plural emitters 35 of the final-stage, or output stage, transistor by aluminum leads 4.
In the prior art circuit configurations, when a reverse bias is applied between the base and the emitter of each Darlington amplifier to turn it off, carriers are not drained uniformly from the vicinities of a bonding pad 51 for the base 32 of the rear-stage transistor shown in FIG. 3(a) and from a portion away from the pad, for example the portion 52. This portion 52, in which carriers concentrate, may not be rapidly turned off but rather keeps conducting, forcing a transitional high carrier current density in the portion 52 of the device during transition periods in operating states. The high current density associated with the on to off transition creates heat, which in turn may destroy the device.
A similar situation occurs between a bonding pad 51 for the base 33 of the final-stage, or output stage, transistor of the three-stage Darlington amplifier shown in FIG. 3(b), and a relatively remote portion 52 opposite pad 51.
It is an object of the invention to provide a Darlington amplifier in which electric current flowing through the base of the output-stage, or final-stage, transistor is less likely to be distributed non-uniformly during transition (turn off) times. It is desired to optimize the current distribution in the semiconductor material of the Darlington configuration so that when the amplifier is turned off, undesirable excess current concentration is reduced in portions where carriers linger, and turn-off conditions are not reached quickly. The goal is to remove carriers uniformly from the base of the output-stage transistor and thereby extend the safe operating region during the application of a reverse bias on said Darlington configuration.